Jobs in Judenburg, Austria
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Principal Engineer Systemverilog And UVM (F/M/Div)
If you''re a motivated and experienced professional looking to take on a challenging role in pre-silicon verification, I encourage you to join our......
Principal Engineer Functional Verification (F/M/Div)
If you''re a motivated and experienced professional looking to take on a challenging role in pre-silicon verification, I encourage you to join our......
Senior Staff Engineer Digital Design (F/M/Div)
Are you passionate about digital design and looking to make a significant impact in a collaborative environment? Do you want to become part of a team......
Engineer Digital Verification Mixed Signal Designs(F/M/Div)
Are you ready to drive innovation, processimprovements, and mentor junior engineers, while fosteringsynergies between digital and analog verification......
Design Application Engineer For Mixed-Signal IC Development(F/M/Div)
As Design Application Engineer for Mixed-signal ICDevelopment you are responsible for providing design support andact as an enabler for IC development......